Dynamic Random Access Memory (DRAM) cells can retain information only temporarily, on the order of milliseconds, even with power continuously applied. Therefore, the cells must be read and refreshed at periodic intervals. Although the storage time may appear to be short, it is actually long enough to allow many memory operations to occur between refresh cycles. The advantages of cost per bit, device density, and flexibility of use (i.e., both read and write operations are possible) have made DRAM cells the most widely used form of semiconductor memory to date. The earliest DRAM cells were three-transistor cells. Today, DRAM cells consisting of only one transistor and one capacitor have been implemented.
As DRAM circuits are scaled to small dimensions, it becomes increasingly important to form compact array cell layouts. The active device transistor is placed along the vertical side wall of a deep-trench storage capacitor in one type of array cell layout. Such a configuration forms a non-planar transistor device.
The non-planar transistor channel region crystal orientation can be a function of lithographic-projected image shape and the overlay between lithographically defined deep trench and active area patterns. Gate oxide thickness, surface state density, and other physical and electrical properties may be a function of the projected image shape and the overlap between the deep trench and active area patterns. These physical and electrical properties influence the transistor electrical, physical, and reliability characteristics.
As shown in FIG. 1, a typical deep trench having an elliptical cross section has a vertical side wall 32 that cuts across a continuum of planes including {001} and {011} crystal planes. Side wall 32 is not aligned with any particular crystal plane. Therefore, side wall 32 has associated crystal-plane-dependent properties that vary as side wall 32 makes a curved transition from one crystallographic plane to the other.
In accordance with standard crystallographic nomenclature, various symbols have specified meanings. Among those symbols are rounded brackets, { }, which refer to families of equivalent crystallographic planes (i.e., the {001} family of planes); parentheses, ( ), which refer to specific crystallographic planes (i.e., the (100) plane); horizontal triangles, &lt; &gt;, which refer to families of equivalent crystallographic axes (i.e., the &lt;011&gt;family of axes); and square brackets, [ ], which refer to a specific crystal axis (i.e., the [110] axis). For example, in silicon crystals, the (100) plane and the (001) plane are equivalent to one another and, thus, are both in the same {001} family of planes.
For optimized device performance, it is desirable to provide a side wall device aligned to a single crystallographic plane having a crystallographic orientation along a single crystal axis. It is an object of the present invention, therefore, to provide a crystal-axis-aligned, non-planar transistor structure. A related object is to provide a process for obtaining such a structure.